Convolutional neural network using VHDL to train an object classifier on an image

• Cesar Arturo Niño Carmonal Universidad Nacional de Piura. Perú http://orcid.org/0000-0002-0981-0822
• Manuel Jesús Sánchez-Chero Universidad Nacional de Frontera http://orcid.org/0000-0003-1646-3037
• Emanuel Ortiz Ortiz Universidad Nacional de Piura. Perú. https://orcid.org/0000-0002-0125-9685
• Juan Carlos Sernaque Julca Universidad Nacional de Piura. Perú. https://orcid.org/0000-0002-3507-9340
• Cecilia Lizeth Risco Ipanaqué Universidad Nacional de Frontera. Perú http://orcid.org/0000-0002-7936-1495

DOI: https://doi.org/10.46925//rdluz.32.16

Keywords: Convolutional Neural Network; FPGA; Python; SoC; VHDL

Abstract

The objective of the present work was to implement a convolutional neural network in hardware using VHDL. Regarding its design, it was experimental, the research begins with the design of a convolutional neural network in Software using Python, where Tensorflow and Keras were used. This design required a 6-epoch training to exceed 90% accuracy when classifying the images from the MNITS dataset. From this design, the parameters and hyperparameters, necessary for hardware design, are obtained. For the implementation of the algorithm in hardware, it was necessary to know the mathematical operation of the convolution, maxpooling and neural network operations, since in the software these operations are summarized in a line of code. Each of these operations was implemented in different blocks, following the modular approach. The response obtained in the hardware is displayed on a screen using the internal communication of the board between the ARM and the FPGA. This response obtained in hardware is similar to that obtained in software and the time in software is much longer than in hardware. The FPGA-based SoC platform, De-10 Nano, was used for this research.

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